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qt 6.6.0 clean
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kleuter
77
util/x86simdgen/3rdparty/simd-intel.conf
vendored
77
util/x86simdgen/3rdparty/simd-intel.conf
vendored
@ -50,13 +50,13 @@ avx512vl Leaf07_00EBX 31 avx512f # AVX512 Vector Length
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avx512vbmi Leaf07_00ECX 1 avx512f # AVX512 Vector Byte Manipulation Instructions
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#pku Leaf07_00ECX 3 # Protection Keys for User mode
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#ospke Leaf07_00ECX 4 # Protection Keys Enabled by OS
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#waitpkg Leaf07_00ECX 5 # User-Level Monitor / Wait
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waitpkg Leaf07_00ECX 5 # User-Level Monitor / Wait
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avx512vbmi2 Leaf07_00ECX 6 avx512f # AVX512 Vector Byte Manipulation Instructions 2
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shstk Leaf07_00ECX 7 # Control Flow Enforcement Technology Shadow Stack
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gfni Leaf07_00ECX 8 # Galois Field new instructions
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vaes Leaf07_00ECX 9 avx2,avx,aes # 256- and 512-bit AES
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#vpclmulqdq Leaf07_00ECX 10 avx # 256- and 512-bit Carryless Multiply
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avx512vnni Leaf07_00ECX 11 avx512f # AVX512 Vector Neural Network Instructions
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#avx512vnni Leaf07_00ECX 11 avx512f # AVX512 Vector Neural Network Instructions
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avx512bitalg Leaf07_00ECX 12 avx512f # AVX512 Bit Algorithms
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avx512vpopcntdq Leaf07_00ECX 14 avx512f # AVX512 Population Count
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#la57 Leaf07_00ECX 16 # 5-level page tables
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@ -78,16 +78,24 @@ hybrid Leaf07_00EDX 15 # Hybrid processor
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ibt Leaf07_00EDX 20 # Control Flow Enforcement Technology Indirect Branch Tracking
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#amxbf16 Leaf07_00EDX 22 amxtile # AMX Tile multiplication in BFloat16
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avx512fp16 Leaf07_00EDX 23 avx512f,f16c # AVX512 16-bit Floating Point
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#amxtile Leaf07_00EDX 24 # Advanced Matrix Extensions Tile support
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#amxint8 Leaf07_00EDX 25 amxtile # AMX Tile multiplication for Int8
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#amx-tile Leaf07_00EDX 24 # Advanced Matrix Extensions Tile support
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#amx-int8 Leaf07_00EDX 25 amx-tile # AMX Tile multiplication for Int8
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raoint Leaf07_01EAX 3 # Remote Atomic Operations, Integer
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#avxvnni Leaf07_01EAX 4 avx # AVX (VEX-encoded) versions of the Vector Neural Network Instructions
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#avx512bf16 Leaf07_01EAX 5 avx512f # AVX512 Brain Float16
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cmpccxadd Leaf07_01EAX 6 # CMPccXADD instructions
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#zlmovsb Leaf07_01EAX 10 # Zero-length MOVSB
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#fsrs Leaf07_01EAX 11 # Fast Short (REP?) STOSB
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#fsrc Leaf07_01EAX 12 # Fast Short (REP?) CMPSB, SCASB
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#fred Leaf07_01EAX 17 # Flexible Return and Event Delivery
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#lkgs Leaf07_01EAX 18 # Load into Kernel GS
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#lam Leaf07_01EAX 26 # Linear Address Masking
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#amx-fp16 Leaf07_01EAX 21 amx-tile # AMX Tile multiplication in FP16
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avxifma Leaf07_01EAX 23 avx # AVX-IFMA instructions
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lam Leaf07_01EAX 26 # Linear Address Masking
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#avxvnniint8 Leaf07_01EDX 4 avx # AVX Vector Neural Network Instructions, Int8
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#avxneconvert Leaf07_01EDX 5 avx # AVX Non-Exception BF16/FP16/FP32 Conversion instructions
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#amx-complex Leaf07_01EDX 8 amx-tile # AMX Complex Matrix multiplication
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#prefetchiti Leaf07_01EDX 14 # PREFETCHIT0/1 instructions
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#xsaveopt Leaf13_01EAX 0 # Optimized XSAVE
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#xsavec Leaf13_01EAX 1 # XSAVE with Compaction
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#xgetbv1 Leaf13_01EAX 2 # XGETBV with ECX=1
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@ -122,12 +130,12 @@ xsave=AvxState SseState|Ymm_Hi128 avx,fma,avx512f
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xsave=MPXState Bndregs|Bndcsr mpx
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xsave=Avx512State AvxState|OpMask|Zmm_Hi256|Hi16_Zmm avx512f
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xsave=CetState CetUState|CetSState shstk
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xsave=AmxState Xtilecfg|Xtiledata amxtile
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xsave=AmxState Xtilecfg|Xtiledata amx-tile
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# Processor/arch listing below this line
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# Source: Intel Instruction Set Extension manual, section 1.2
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# Source: GCC gcc/config/i386/i386.h, i386-c.c, i386-builtins.c
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# Architecture Based on New features Optional features
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# Architecture Based on New features
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arch=x86_64 <> sse2
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# Core line
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arch=Core2 x86_64 sse3,ssse3,cx16
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@ -135,26 +143,44 @@ arch=NHM Core2 sse4.1,sse4.2,popcnt
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arch=WSM NHM
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arch=SNB WSM avx
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arch=IVB SNB f16c,rdrnd,fsgsbase
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arch=HSW IVB avx2,fma,bmi,bmi2,lzcnt,movbe
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arch=HSW IVB avx2,fma,bmi,bmi2,lzcnt,movbe # hle,rtm
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arch=BDW HSW adx,rdseed
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arch=BDX BDW
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arch=SKL BDW xsavec,xsaves
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arch=ADL SKL avxvnni,gfni,vaes,vpclmulqdq,serialize,shstk,cldemote,movdiri,movdir64b,ibt,waitpkg,keylocker rdpid
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arch=SKX SKL avx512f,avx512dq,avx512cd,avx512bw,avx512vl clwb
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arch=SKX SKL avx512f,avx512dq,avx512cd,avx512bw,avx512vl #clwb
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arch=CLX SKX avx512vnni
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arch=CPX CLX avx512bf16
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arch=CNL SKX avx512ifma,avx512vbmi sha
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arch=ICL CNL avx512vbmi2,gfni,vaes,vpclmulqdq,avx512vnni,avx512bitalg,avx512vpopcntdq fsrm,rdpid
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arch=ICX ICL pconfig
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arch=TGL ICL avx512vp2intersect,shstk,,movdiri,movdir64b,ibt,keylocker
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arch=SPR TGL avx512bf16,amxtile,amxbf16,amxint8,avxvnni,cldemote,pconfig,waitpkg,serialize,tsxldtrk,uintr
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arch=PLC SKX avx512ifma,avx512vbmi #sha
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arch=SNC PLC avx512vbmi2,gfni,vaes,vpclmulqdq,avx512vnni,avx512bitalg,avx512vpopcntdq #fsrm,rdpid
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arch=WLC SNC shstk,movdiri,movdir64b,ibt,keylocker # avx512vp2intersect
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arch=GLC WLC avx512bf16,avxvnni,cldemote,waitpkg,serialize,uintr # tsxldtrk
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arch=RPC GLC
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arch=RWC RPC prefetchiti
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# Atom line
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arch=SLM WSM rdrnd,movbe
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arch=GLM SLM fsgsbase,rdseed,lzcnt,xsavec,xsaves
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arch=TNT GLM clwb,gfni,cldemote,waitpkg,movdiri,movdir64b
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arch=GRT SKL avxvnni,gfni,vaes,vpclmulqdq,serialize,shstk,cldemote,movdiri,movdir64b,ibt,waitpkg,keylocker # rdpid
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arch=CMT GRT cmpccxadd,avxifma,avxneconvert,avxvnniint8
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# Xeon Phi line
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#arch=KNL SKL avx512f,avx512er,avx512pf,avx512cd
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#arch=KNM KNL avx5124fmaps,avx5124vnniw,avx512vpopcntdq
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# Hybrids and other names
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arch=CNL PLC
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arch=ICL SNC
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arch=TGL WLC
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arch=ADL GRT
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arch=RPL GRT
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arch=MTL CMT
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arch=ARL CMT
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arch=LNL CMT
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arch=ICX SNC pconfig
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arch=SPR GLC pconfig,amx-tile,amx-bf16,amx-int8
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arch=EMR SPR
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arch=GNR GLC pconfig,amx-tile,amx-bf16,amx-int8,amx-fp16,amx-complex
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arch=SRF CMT cmpccxadd,avxifma,avxneconvert,avxvnniint8
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arch=GRR SRF raoint
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arch=CWF SRF
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# Longer names
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arch=Nehalem NHM # Intel Core i3/i5/i7
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arch=Westmere WSM # Intel Core i3/i5/i7
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@ -166,14 +192,31 @@ arch=Skylake SKL # Sixth Generation Intel Core i3/i5/i7
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arch=Skylake-Avx512 SKX # Intel Xeon Scalable
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arch=CascadeLake CLX # Second Generation Intel Xeon Scalable
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arch=CooperLake CPX # Third Generation Intel Xeon Scalable
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arch=PalmCove PLC
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arch=CannonLake CNL # Intel Core i3-8121U
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arch=SunnyCove SNC
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arch=IceLake-Client ICL # Tenth Generation Intel Core i3/i5/i7
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arch=IceLake-Server ICX # Third Generation Intel Xeon Scalable
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arch=AlderLake ADL
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arch=SapphireRapids SPR
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arch=WillowCove WLC
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arch=TigerLake TGL # Eleventh Generation Intel Core i3/i5/i7
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arch=GoldenCove GLC
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arch=AlderLake ADL # Twelfth Generation Intel Core
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arch=RaptorCove RPC
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arch=RaptorLake RPL # Thirteenth Generation Intel Core
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arch=RedwoodCove RWC
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arch=MeteorLake MTL
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arch=ArrowLake ARL
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arch=LunarLake LNL
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arch=SapphireRapids SPR # Fourth Generation Intel Xeon Scalable
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arch=EmeraldRapids EMR # Fifth Generation Intel Xeon Scalable
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arch=GraniteRapids GNR
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arch=Silvermont SLM
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arch=Goldmont GLM
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arch=Tremont TNT
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arch=Gracemont GRT
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arch=Crestmont CMT
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arch=GrandRidge GRR
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arch=SierraForest SRF
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arch=ClearwaterForest CWF
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#arch=KnightsLanding KNL
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#arch=KnightsMill KNM
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5
util/x86simdgen/3rdparty/x86simd_generate.pl
vendored
5
util/x86simdgen/3rdparty/x86simd_generate.pl
vendored
@ -13,6 +13,7 @@ my %leaves = (
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Leaf07_00ECX => "CPUID Leaf 7, Sub-leaf 0, ECX",
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Leaf07_00EDX => "CPUID Leaf 7, Sub-leaf 0, EDX",
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Leaf07_01EAX => "CPUID Leaf 7, Sub-leaf 1, EAX",
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Leaf07_01EDX => "CPUID Leaf 7, Sub-leaf 1, EDX",
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Leaf13_01EAX => "CPUID Leaf 13, Sub-leaf 1, EAX",
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Leaf80000001hECX => "CPUID Leaf 80000001h, ECX",
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Leaf80000008hEBX => "CPUID Leaf 80000008h, EBX",
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@ -258,7 +259,7 @@ print "\nenum X86CpuidLeaves {";
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map { print " $_," } @leafNames;
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print " X86CpuidMaxLeaf\n};";
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my $type = scalar %leaves > 8 ? "uint16_t" : "uint8_t";
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my $type = scalar keys %leaves > 8 ? "uint16_t" : "uint8_t";
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printf "\nstatic const %s x86_locators[] = {\n",
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$type, $type;
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for (my $j = 0; $j < scalar @features; ++$j) {
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@ -283,7 +284,7 @@ struct X86Architecture
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};
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static const struct X86Architecture x86_architectures[] = {|;
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for (sort { $b <=> $a } keys %sorted_archs) {
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for (sort keys %sorted_archs) {
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my $arch = $sorted_archs{$_};
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next if $arch->{base} eq "<>";
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printf " { cpu_%s, \"%s\" },\n", $arch->{id}, $arch->{prettyname};
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@ -14,9 +14,7 @@ $(TARGETDIR)/$(TARGETHEADER): header $(TARGETHEADER)
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sed '/-- implementation start --/,/-- implementation end --/d' $^ | \
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sed 's!3rdparty/x86simd_generate\.pl!util/x86simdgen/README.md!' > $@
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$(TARGETDIR)/$(TARGETCPP): $(TARGETHEADER) header
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(cat header | grep -v '^//' | grep .; echo; \
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echo '// This is a generated file. DO NOT EDIT.'; \
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echo '// Please see util/x86simdgen/README.md'; \
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(sed '/^$$/q' header; \
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echo '#include "$(TARGETHEADER)"'; \
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sed '1,/-- implementation start --/d;/-- implementation end --/,$$d' $<) > $@
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@ -1,5 +1,7 @@
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// Copyright (C) 2022 Intel Corporation.
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// SPDX-License-Identifier: LicenseRef-Qt-Commercial OR LGPL-3.0-only OR GPL-2.0-only OR GPL-3.0-only
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// This is a generated file. DO NOT EDIT.
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// Please see util/x86simdgen/README.md
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//
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// W A R N I N G
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